Integrated circuit memory devices are being developed with increasingly higher levels of integration in order to-increase the memory capacity of these devices. Accordingly, the size of each unit memory cell within an integrated circuit memory device is reduced. The thicknesses of the layers used to form the memory cells, however, are not necessarily reduced in proportion to the reduction of the size of the memory cell. The vertical structure of these smaller memory cells may thus become more complicated as the ratio of layer thicknesses to cell size increases.
In particular, dynamic random access memories (DRAM) are typically developed with levels of integration which are higher than that of other integrated circuit memory devices. Furthermore, the capacitor of a DRAM memory cell is usually formed after forming the bit-lines of the DRAM to increase the effective area of the capacitor. Accordingly, an electrical connection must be provided from the capacitor to the source region of a transistor on the substrate, and this electrical connection is typically formed after forming the gate-lines, the bit-lines, and various insulating layers. Accordingly, with highly integrated dynamic random access memories, this electrical connection generally must be provided between bit-lines which are more closely spaced and through layers which have not decreased in thickness at the same rate as the decrease in space between bit-lines.
A plan view of a conventional dynamic random access memory including a buried contact hole is illustrated in FIG. 1. Sectional views of the DRAM of FIG. 1 are illustrated in FIGS. 2 and 3. In particular, FIG. 2 is taken along section line AA' of FIG. 1, and FIG. 3 is taken along section line BB' of FIG. 1.
As shown, each memory cell is formed on a region of the substrate 1 including a source region 5, a drain region 7, and a channel region therebetween. A plurality of gate-lines 3 are formed on the substrate, and each of the gate-lines 3 is located adjacent a channel region. In particular, each gate-line includes an insulating layer adjacent the substrate and a conductive layer on the insulating layer opposite the substrate. Each drain region 7 is electrically connected to a respective bit-line 11 through an auxiliary conductive layer pattern 9. An insulating film 13 is formed over the substrate 1 and the gate-lines 3.
A photoresist pattern 15 is formed on the insulating layer 13. This pattern is used as a mask to etch buried contact holes 17 through the insulating layer 13 thus exposing the source regions 5 of the transistors formed in the substrate. The contact hole 17 can then be used to provide electrical connection between the source regions and respective memory cell capacitors.
A plan view of the photoresist pattern 15 used to etch the buried contact holes 17 is illustrated in FIG. 4. In particular, the photoresist pattern includes openings corresponding to the contact holes 17 to be etched. These contact holes must be relatively small and precisely aligned relative to the source regions in order to etch through the insulating layers without exposing the bit-lines 11 or the gate-lines 3.
As the size of the memory cell is reduced, however, the size of the holes in the photoresist pattern 15 must also be reduced. This reduction in the size of the holes in the photoresist pattern may be limited, however, by the photolithography process used to pattern the photoresist. Furthermore, the alignment margin for the photoresist pattern decreases as the size of the memory cell is reduced resulting in a greater likelihood of failure due to misalignment. In addition, as the size of the memory cell decreases without corresponding reductions in the thicknesses of the layers, the etching process may become more difficult to perform.